1. Field of the Invention
The present invention relates to a semiconductor device and to a method of fabricating the same. More particularly, it relates to semiconductor device suitably applicable to a nonvolatile semiconductor memory in which a floating gate and a control gate are formed via a dielectric film.
2. Description of the Related Art
Recently, a nonvolatile memory such as an EEPROM which holds stored data even when disconnected from a power supply has attracted attention as a semiconductor memory. In this nonvolatile memory, a floating gate is formed on a semiconductor substrate via a tunnel insulating film, and a control gate is formed as to oppose this floating gate via a dielectric film.
One example of this nonvolatile semiconductor memory is disclosed in Japanese Patent Laid-Open No. 6-85279. This element is obtained by turning the above nonvolatile semiconductor memory upside down. More specifically, this nonvolatile semiconductor memory is fabricated by sequentially stacking a gate insulating film, a floating gate, and a tunnel insulating film in an insulating film formed on a semiconductor substrate, and forming a semiconductor layer having a source and a drain on top of the resultant structure. Since contacts can be extracted from the upper surface side, this element facilitates arranging word lines and is suited to increase the degree of integration.
However, the structure of this nonvolatile semiconductor memory is complicated because the memory has a stacked gate structure, and this extremely increases the accuracy requirements when the element is to be formed. In addition, to lower the write voltage, it is necessary to increase the area of the overlap of the control gate and the floating gate. This not only increases the number of fabrication steps and the fabrication cost and lowers the reliability but also interferes with an increase in the degree of integration.
To solve the above problems, Japanese Patent Laid-Open No. 59-155968 or Japanese Patent Publication No. 7-112018 has disclosed an EEPROM which has a small cell area and includes a single-layer polysilicon film. This EEPROM includes a first element active region formed by forming a source and a drain on a semiconductor substrate and a second element active region formed adjacent to the first element active region via an element isolation structure by forming an impurity diffusion layer. A single-layer polysilicon film is patterned to form a floating gate which Is formed by patterning on a channel between the source and the drain via a tunnel insulating film in the first element active region. This floating gate is formed by patterning to oppose the impurity diffusion layer via a gate insulating film in the second active region. The impurity diffusion layer in the second element active region functions as a control gate.
In the above single-layer gate EEPROM, however, it is necessary to apply a high voltage of 20 (V) or more to the control gate, i.e., the impurity diffusion layer when data is erased or written, especially when data is erased. Consequently, it becomes difficult to ensure a large enough breakdown voltage between the control gate and the semiconductor substrate, leading to a serious problem of an operation error.
Furthermore, Japanese Patent Laid-Open No. 7-147340 has disclosed an EEPROM which has a diffusion layer serving as the control gate separated from other semiconductor area to apply a high voltage to the diffusion layer.
However, it is difficult to minimize variations in the threshold value of the EEPROM and stably perform write and read operations.